?2011 fairchild semiconductor corporation aug 2011 fdd26an06a0_f085 rev. c1 fdd26an06a0_f085 " n-channel powertrench ? mosfet 60v, 36a, 26m ? features ?r ds(on) = 20m ? (typ.), v gs = 10v, i d = 36a q g (tot) = 13nc (typ.), v gs = 10v low miller charge low q rr body diode uis capability (single pulse and repetitive pulse) qualified to aec q101 applications motor / body load control abs systems powertrain management injection systems dc-dc converters and off-line ups distributed power architectures and vrms primary switch for 12v and 24v systems mosfet maximum ratings t c = 25c unless otherwise noted thermal characteristics this product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. for a copy of the requirements, see aec q101 at: http://www.aecouncil.com/ all fairchild semiconductor products are manufactured, assembled and tested under iso9000 and qs9000 quality systems certification. symbol parameter ratings units v dss drain to source voltage 60 v v gs gate to source voltage 20 v i d drain current 36 a continuous (t c = 25 o c, v gs = 10v) continuous (t c = 100 o c, v gs = 10v) 25 a continuous (t amb = 25 o c, v gs = 10v, r ja = 52 o c/w) 7 a pulsed figure 4 a e as single pulse avalanche energy ( note 1) 35 mj p d power dissipation 75 w derate above 25 o c0.5w/ o c t j , t stg operating and storage temperature -55 to 175 o c r jc thermal resistance junction to case to-252 2.0 o c/w r ja thermal resistance junction to ambient to-252 100 o c/w r ja thermal resistance junction to ambient to-252, 1in 2 copper pad area 52 o c/w d g s to-252aa fdd series gate source (flange) drain fdd26an06a0_f085 rohs compliant n-channel powertrench ? mosfet
?2011 fairchild semiconductor corporation fdd26an06a0_f085 rev. c1 fdd26an06a0_f085 package marking and ordering information electrical characteristics t c = 25c unless otherwise noted off characteristics on characteristics dynamic characteristics switching characteristics (v gs = 10v) drain-source diode characteristics notes: 1: starting t j = 25c, l = 83 h, i as = 29a, v dd = 54v, v gs = 10v. device marking device package reel size tape width quantity fdd26an06a0 fdd26an06a0_f085 to-252aa 330mm 16mm 2500 units symbol parameter test conditions min typ max units b vdss drain to source breakdown voltage i d = 250 a, v gs = 0v 60 - - v i dss zero gate voltage drain current v ds = 50v - - 1 a v gs = 0v t c = 150 o c - - 250 i gss gate to source leakage current v gs = 20v - - 100 na v gs(th) gate to source threshold voltage v gs = v ds , i d = 250 a2-4v r ds(on) drain to source on resistance i d = 36a, v gs = 10v - 0.020 0.026 ? i d = 36a, v gs = 10v, t j = 175 o c - 0.045 0.058 c iss input capacitance v ds = 25v, v gs = 0v, f = 1mhz - 800 - pf c oss output capacitance - 155 - pf c rss reverse transfer capacitance - 55 - pf q g(tot) total gate charge at 10v v gs = 0v to 10v v dd = 30v i d = 36a i g = 1.0ma -1317nc q g(th) threshold gate charge v gs = 0v to 2v - 1.7 2.2 nc q gs gate to source gate charge - 4.3 - nc q gs2 gate charge threshold to plateau - 2.6 - nc q gd gate to drain ?miller? charge - 4.6 - nc t on tu r n - o n t i m e v dd = 30v, i d = 36a v gs = 10v, r gs = 25 ? - - 123 ns t d(on) turn-on delay time - 9 - ns t r rise time - 72 - ns t d(off) turn-off delay time - 23 - ns t f fall time - 35 - ns t off turn-off time - - 88 ns v sd source to drain diode voltage i sd = 36a - - 1.25 v i sd = 18a - - 1.0 v t rr reverse recovery time i sd = 36a, di sd /dt = 100a/ s- -43ns q rr reverse recovered charge i sd = 36a, di sd /dt = 100a/ s- -50nc n-channel powertrench ? mosfet
?2011 fairchild semiconductor corporation fdd26an06a0_f085 rev. c1 fdd26an06a0_f085 typical characteristics t c = 25c unless otherwise noted figure 1. normalized power dissipation vs case temperature figure 2. maximum continuous drain current vs case temperature figure 3. normalized maximum transient thermal impedance figure 4. peak current capability t c , case temperature ( o c) power dissipation multiplier 0 0 25 50 75 100 175 0.2 0.4 0.6 0.8 1.0 1.2 125 150 0 10 20 30 40 25 50 75 100 125 150 175 i d , drain current (a) t c , case temperature ( o c) 0.1 1 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 0.01 2 t, rectangular pulse duration (s) z jc , normalized thermal impedance notes: duty factor: d = t 1 /t 2 peak t j = p dm x z jc x r jc + t c p dm t 1 t 2 0.5 0.2 0.1 0.05 0.01 0.02 duty cycle - descending order single pulse 100 500 30 i dm , peak current (a) t, pulse width (s) 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 t c = 25 o c i = i 25 175 - t c 150 for temperatures above 25 o c derate peak current as follows: transconductance may limit current in this region v gs = 10v n-channel powertrench ? mosfet
?2011 fairchild semiconductor corporation fdd26an06a0_f085 rev. c1 fdd26an06a0_f085 figure 5. forward bias safe operating area note: refer to fairchild application notes an7514 and an7515 figure 6. unclamped inductive switching capability figure 7. transfer characteristics figure 8. saturation characteristics figure 9. drain to source on resistance vs drain current figure 10. normalized drain to source on resistance vs junction temperature typical characteristics t c = 25c unless otherwise noted 0.1 1 10 100 1000 110 100 v ds , drain to source voltage (v) i d , drain current (a) t j = max rated t c = 25 o c single pulse limited by r ds(on) area may be operation in this 10 s 1ms dc 100 s 10ms 1 10 100 0.01 0.1 1 300 10 i as , avalanche current (a) t av , time in avalanche (ms) starting t j = 25 o c starting t j = 150 o c t av = (l)(i as )/(1.3*rated bv dss - v dd ) if r = 0 if r 0 t av = (l/r)ln[(i as *r)/(1.3*rated bv dss - v dd ) +1] 0 20 40 60 80 100 3456789 i d , drain current (a) v gs , gate to source voltage (v) pulse duration = 80 s duty cycle = 0.5% max v dd = 15v t j = 175 o c t j = 25 o c t j = -55 o c 0 20 40 60 80 100 01234 i d , drain current (a) v ds , drain to source voltage (v) v gs = 5v v gs = 20v v gs = 7v pulse duration = 80 s duty cycle = 0.5% max t c = 25 o c v gs = 10v v gs = 6v 18.0 18.5 19.0 19.5 20.0 0 10203040 i d , drain current (a) v gs = 10v drain to source on resistance(m ? ) pulse duration = 80 s duty cycle = 0.5% max 0.5 1.0 1.5 2.0 2.5 -80 -40 0 40 80 120 160 200 normalized drain to source t j , junction temperature ( o c) on resistance v gs = 10v, i d = 36a pulse duration = 80 s duty cycle = 0.5% max n-channel powertrench ? mosfet
?2011 fairchild semiconductor corporation fdd26an06a0_f085 rev. c1 fdd26an06a0_f085 figure 11. normalized gate threshold voltage vs junction temperature figure 12. normalized drain to source breakdown voltage vs junction temperature figure 13. capacitance vs drain to source voltage figure 14. gate charge waveforms for constant gate current typical characteristics t c = 25c unless otherwise noted 0.4 0.6 0.8 1.0 1.2 -80 -40 0 40 80 12 160 200 v gs = v ds , i d = 250 a normalized gate t j , junction temperature ( o c) threshold voltage 0.90 0.95 1.00 1.05 1.10 1.15 -80 -40 0 40 80 120 160 200 t j , junction temperature ( o c) normalized drain to source i d = 250 a breakdown voltage 100 1000 0.1 1 10 60 2000 30 c, capacitance (pf) v ds , drain to source voltage (v) v gs = 0v, f = 1mhz c iss = c gs + c gd c oss ? c ds + c gd c rss = c gd 0 2 4 6 8 10 0 2 4 6 8 10 12 14 v gs , gate to source voltage (v) q g , gate charge (nc) v dd = 30v i d = 36a i d = 7a waveforms in descending order: n-channel powertrench ? mosfet
?2011 fairchild semiconductor corporation fdd26an06a0_f085 rev. c1 fdd26an06a0_f085 test circuits and waveforms figure 15. unclamped energy test circuit figure 16. unclamped energy waveforms figure 17. gate charge test circuit figure 18. gate charge waveforms figure 19. switching time test circuit figure 20. switching time waveforms t p v gs 0.01 ? l i as + - v ds v dd r g dut vary t p to obtain required peak i as 0v v dd v ds bv dss t p i as t av 0 v gs + - v ds v dd dut i g(ref) r l v dd q g(th) v gs = 2v q gs2 q g(tot) v gs = 10v v ds v gs i g(ref) 0 0 q gs q gd v gs r l r gs dut + - v dd v ds v gs t on t d(on) t r 90% 10% v ds 90% 10% t f t d(off) t off 90% 50% 50% 10% pulse width v gs 0 0 n-channel powertrench ? mosfet
?2011 fairchild semiconductor corporation fdd26an06a0_f085 rev. c1 fdd26an06a0_f085 thermal resistance vs. mounting pad area the maximum rated junction temperature, t jm , and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, p dm , in an application. therefore the application?s ambient temperature, t a ( o c), and thermal resistance r ja ( o c/w) must be reviewed to ensure that t jm is never exceeded. equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. in using surface mount devices such as the to-252 package, the environment in which it is applied will have a significant influence on the part?s current and maximum power dissipation ratings. precise determination of p dm is complex and influenced by many factors: 1. mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. the number of copper layers and the thickness of the board. 3. the use of external heat sinks. 4. the use of thermal vias. 5. air flow and board orientation. 6. for non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. fairchild provides thermal information to assist the designer?s preliminary application evaluation. figure 21 defines the r ja for the device as a function of the top copper (component side) area. this is for a horizontally positioned fr-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. this graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. pulse applications can be evaluated using the fairchild device spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. thermal resistances corresponding to other copper areas can be obtained from figure 21 or by calculation using equation 2 or 3. equation 2 is used for copper area defined in inches square and equation 3 is for area in centimeters square. the area, in square inches or square centimeters is the top copper area including the gate and source pads. (eq. 1) p dm t jm t a ? () r ja ----------------------------- = area in inches squared (eq. 2) r ja 33.32 23.84 0.268 area + () ------------------------------------ - + = (eq. 3) r ja 33.32 154 1.73 area + () ---------------------------------- + = area in centimeters squared 25 50 75 100 125 0.01 0.1 1 10 figure 21. thermal resistance vs mounting pad area r ja = 33.32+ 23.84/(0.268+area) eq.2 r ja ( o c/w) area, top copper area in 2 (cm 2 ) r ja = 33.32+ 154/(1.73+area) eq.3 (0.645) (6.45) (64.5) (0.0645) n-channel powertrench ? mosfet
trademarks the following includes registered and unregistered trademarks and service marks, owned by fairchild semiconductor and/or its gl obal subsidiaries, and is not intended to be an exhaustive list of all such trademarks. *trademarks of system general corporation, used under license by fairchild semiconductor. disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function, or design. fairchild does not assume an y liability arising out of the application or use of any product or circuit described herein; neither does it convey an y license under its patent rights, nor the rights of others. these specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers these products. life support policy fairchild?s products are not authorized for use as critical co mponents in life support devices or systems without the express written approval of fa irchild semiconductor corporation. as used here in: 1. life support devices or systems ar e devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a signi ficant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms 2cool? accupower? auto-spm? ax-cap?* bitsic ? build it now? coreplus? corepower? crossvolt ? ctl? current transfer logic? deuxpeed ? dual cool? ecospark ? efficentmax? esbc? fairchild ? fairchild semiconductor ? fact quiet series? fact ? fast ? fastvcore? fetbench? flashwriter ? * fps? f-pfs? frfet ? global power resource sm green fps? green fps? e-series? g max ? gto? intellimax? isoplanar? megabuck? microcoupler? microfet? micropak? micropak2? millerdrive? motionmax? motion-spm? mwsaver? optihit? optologic ? optoplanar ? ? pdp spm? power-spm? powertrench ? powerxs? programmable active droop? qfet ? qs? quiet series? rapidconfigure? saving our world, 1mw/w/kw at a time? signalwise? smartmax? smart start? spm ? stealth? superfet ? supersot?-3 supersot?-6 supersot?-8 supremos ? syncfet? sync-lock? ?* the power franchise ? the right technology for your success? ? tinyboost? tinybuck? tinycalc? tinylogic ? tinyopto? tinypower? tinypwm? tinywire? transic ? trifault detect? truecurrent ? * serdes? uhc ? ultra frfet? unifet? vcx? visualmax? xs? tm ? tm ? tm datasheet identification product status definition advance information formative / in design datasheet contains the design specifications for product development. specifications may change in any manner without notice. preliminary first production datasheet contains preliminary data; supp lementary data will be published at a later date. fairchild semiconductor reserves the ri ght to make changes at any time without notice to improve design. no identification needed full production datasheet contains final specifications. fair child semiconductor reserves the right to make changes at any time without notice to improve the design. obsolete not in production datasheet contains specifications on a product t hat is discontinued by fairchild semiconductor. the datasheet is for reference information only. anti-counterfeiting policy fairchild semiconductor corporation?s anti-counterfeiting policy. fairchild?s anti-counterfeiting policy is also stated on our external website, www.fairchildsemi.com, under sales support . counterfeiting of semiconductor parts is a growing problem in th e industry. all manufactures of semiconductor products are expe riencing counterfeiting of their parts. customers who inadvertently purchase counterfeit parts ex perience many problems such as loss of brand reputation, substa ndard performance, failed application, and increased cost of production and manufacturing dela ys. fairchild is taking strong measures to protect ourselve s and our customers from the proliferation of counterfeit parts. fairchild strongly encourages customers to purchase fairchild parts either directly from fa irchild or from authorized fairchild distributors who are listed by c ountry on our web page cited above. products customers buy either from fairchild directly or fr om authorized fairchild distributors are genuine parts, have full traceability, meet fairchild?s quality standards for handing and storage and provide access to fairchild?s full range of up-to-date technical and product information. fairchild and our authorized distributors will stand behind all warranties and wi ll appropriately address and warranty issues that may arise. fairchild will not provide any warranty coverage or other assistance for parts bought from unau thorized sources. fairchild is committed to combat this global problem and encourage our customers to do their part in stopping this practice by buying direct or from authorized distributors. rev. i55
|
